A common requirement for semiconductor processing of integrated circuits is formation of capacitors. Because the gates for MOS transistors lie over a dielectric material, these structures are also used as capacitors. The gate material can form one plate of capacitor, the dielectric material can form the capacitor dielectric, and the second plate of the capacitor may be formed by a doped conductive region in the substrate beneath the dielectric. MOS capacitors are particularly useful as capacitors that may be implemented on integrated circuits that also feature, for example, MOS transistors, resistors, memory cells, and other logic and circuit devices.
Recently the use of metal material as the gate conductors with high-k gate dielectrics has become more prevalent in “high-k metal gate” or “HKMG” semiconductor processes. As the metal gate conductors lie over a dielectric layer, MOS capacitors may be formed by using the metal gate conductor of the HKMG device as a first plate, the high-k dielectric material as the capacitor dielectric, and the second plate may be formed beneath the dielectric, for example by doping the substrate to form a conductive region. In this manner metal gate MOS capacitors may be formed in a HKMG replacement gate process. The metal gate material may be formed in a replacement gate process by replacing a previously formed dummy gate. The dummy gates are formed earlier in the process and may be used for certain process steps. Then, using photolithography pattern and etch steps to remove the dummy gates and the original gate dielectric, the replacement gate process exposes a gate trench area in an interlevel dielectric layer. High-k dielectrics may be used to form the dielectric in the replacement gate region. The metal replacement gate can be formed in a variety of ways, for example by deposition or plating, and then removing excess metal in a chemical mechanical polishing (CMP) process.
However, in order to obtain a capacitance of a useful value, a large area metal gate device, or many metal gate devices in a small area would be required. In the metal gate replacement processes, CMP loading effects can occur when the metal pattern exceeds a certain pattern density in a given area being processed. In CMP loading, dishing of the top portion of gate metal material has been observed during the CMP processing. The dishing is a defect and causes reduced device yields and increasing costs. This makes the use of MOS capacitors formed using metal replacement gate HKMG devices more costly, or even impractical.
The drawings, schematics and diagrams are illustrative and not intended to be limiting, but are examples of embodiments of the invention, are simplified for explanatory purposes, and are not drawn to scale.